Silicon carbide (SiC) is a widely used semiconductor material for power semiconductor devices due to its high blocking voltage and its capability to operate reliably at high temperatures. An important parameter that influences the overall device performance is the so-called on-resistance Ron, which is mainly governed by the resistance of the drift region and of the channel region. In order to reduce the resistance of the channel region attempts have been made to include a graphene layer as part of the channel region. While the formation of a graphene layer on plane surfaces of semiconductor materials has attracted much attention, the formation of graphene on structured surfaces is technologically still difficult.
Furthermore, semiconductor devices with a vertical current flow can include trenches with side walls along which the channel regions are formed. Depending on the rated blocking voltage of the semiconductor device the vertical thickness of the semiconductor material must be adapted. In a typical application, the final vertical thickness of the semiconductor material is significantly less than 1 mm. During manufacturing, the handling of semiconductor wafers having such a low thickness is demanding as the semiconductor material is brittle and can easily break.
For those applications, typically a carrier wafer is attached to the semiconductor wafer prior to reducing the thickness of the semiconductor wafer down to the desired vertical thickness. Mechanical processes such as grinding or polishing are currently commonly used to reduce the thickness of the semiconductor wafers. These processes, however, waste much semiconductor material which leads to an increase of manufacturing costs. Furthermore, the carrier materials which are typically used, and the bond connections between the carrier material and the semiconductor wafer, do not withstand high temperatures which may be needed to form graphene layers.
In view of the above there is need for improvement.